The present invention relates generally to methods for identifying, during the design stage of integrated circuits (ICs) and semiconductor wafers, electrical properties likely to cause defects in those devices when manufactured, and more specifically to visually displaying those potential defects such that they are more easily identified.
Integrated circuit design can be divided into three stages: circuitry as specified, circuitry as designed and circuitry as manufactured.
Circuitry as specified is a somewhat abstracted circuit design made with knowledge of the latest state of the art integrated circuit manufacturing capabilities. It represents what a designer wants the chip to do. The final output of the circuitry as specified process typically is a register transfer level (RTL) description, or RTL design.
Circuitry as designed is a computer generated representation of the physical layout of an IC designed to achieve the goals of the circuitry as specified design. It's typically developed using such computer tools as CADENCE software. The final output of the circuitry as designed process is a so-called tapeout file ready to be sent to an IC foundry to be made into physical ICs.
Circuitry as manufactured is, of course, final manufactured ICs.
Because both circuitry as specified and circuitry as designed stages are performed pushing the envelope, so to speak, of then latest state of the art IC manufacturing capabilities, defects, both actual and potential, often occur. It's desirable, of course, to detect those defects as early in the design process as possible, preferably during the circuitry as designed stage and not after the circuitry as manufactured stage.
Unfortunately, when commercially available additional software is applied to the circuitry as designed process to identify resulting electrical properties, the output files typically are huge ASCII files suitable for printing only on numerous sheets of 14 inch perforated green bar paper. They are both difficult to read and overwhelming.
U.S. Pat. No. 7,260,810 to Filippi, Jr., et al. describes analyzing circuitry as designed designs by discretizing a design structure into pixel elements representative of the physical design structure and determining at least one physical structural property from each pixel element. Each pixel element corresponds generally to a portion of an IC chip area.
The Filippi, Jr., et al. invention is very broadly described, including many broadly claimed variations, but with very little description of any details required to implement either its most general description or any of the claimed variations.
Related U.S. Pat. No. 7,346,470 to Wisniewski (now Lanzerotti) et al. and U.S. Pat. No. 7,752,581 to Lanzerotti et al. describe methods for identifying high risk factors in circuit design data, including by correlating actual defects in as manufactured ICs and semiconductor wafers with original circuit design data.
The two Lanzerotti et al. patents do not describe how to then best use that information for spotlighting those high risk factors in circuit design data during the circuitry as designed stage. Nor do they describe methods for identifying high risk factors in circuit design data without having to first manufacture the ICs to reveal defects.
All three of U.S. Pat. Nos. 7,260,810, 7,346,470 and 7,752,581 are incorporated by reference into this description.
There is, therefore, a need for better approaches for identifying high risk factors in IC circuit designs during the circuitry as designed stage and spotlighting those high risk factors for faster and easier identification by designers.